This visual model shows how the CPU translates a virtual address into a physical address before accessing memory.
CPU Virtual Address
|
v
TLB Lookup
|
+-----+-----+
| |
| |
TLB HIT TLB MISS
| |
| v
| Page Table Walk
| |
| v
| Locate Mapping
| |
| v
| Update TLB
| |
+-----------+
|
v
Physical Address
|
v
Access RAM
The Translation Lookaside Buffer (TLB) is a small cache that stores recent virtual-to-physical address translations.
On a TLB hit, the CPU immediately obtains the physical address. On a TLB miss, the CPU must walk the page tables, locate the mapping, update the TLB, and then continue execution.
Because memory references occur constantly, TLB performance has a major impact on overall system speed.