The TLB, or Translation Lookaside Buffer,
is a small, fast cache inside the CPU that stores recent virtual-to-physical
address translations.
It exists because every memory access needs address translation, and doing
a full page-table walk every time would be far too slow.
The TLB is not a cache of data. It is a cache of address translations.
It helps the CPU quickly answer: “Where is this virtual address in physical memory?”
Why Address Translation Is Needed
Linux processes use virtual addresses.
Physical RAM uses physical addresses.
When a program accesses memory, the CPU must translate the virtual address
into a physical address before the memory can actually be reached.
Process uses virtual address
↓
CPU must translate it
↓
Physical address found
↓
Memory can be accessed
The page tables contain the translation information, but walking page tables
takes time.
The Problem Without a TLB
A program may perform millions or billions of memory accesses.
If each access required a full page-table walk, memory access would become
painfully expensive.
Without the TLB, the CPU would spend far too much time looking up addresses
instead of executing program instructions.
What the TLB Stores
The TLB stores recently used translations.
Virtual Page Number → Physical Page Number
Virtual Page Number → Physical Page Number
Virtual Page Number → Physical Page Number
When the CPU needs to translate an address, it checks the TLB first.
TLB Hit
A TLB hit means the needed translation is already in the TLB.
CPU has virtual address
↓
Check TLB
↓
Translation found
↓
Use physical address immediately
A TLB hit is the fast path. The CPU avoids walking the page tables.
TLB Miss
A TLB miss means the translation is not currently cached.
CPU has virtual address
↓
Check TLB
↓
Translation not found
↓
Walk page tables
↓
Load translation into TLB
↓
Continue memory access
A TLB miss is not the same thing as a page fault.
The page may be valid and present; the CPU simply did not have the translation cached.
A TLB miss means “translation not cached.”
A page fault means “memory page not immediately usable.”
Relationship to Page Faults
Page faults and TLB misses both happen during memory access, but they solve
different problems.
Memory access
↓
Need address translation
↓
Check TLB
↓
If TLB miss: walk page tables
↓
If page not ready: page fault
The TLB speeds up normal memory access. Page faults handle cases where the
memory page itself is not ready, not mapped, or not permitted.
Why Locality Matters
Programs often reuse nearby memory addresses.
This is called locality.
Temporal locality: recently used memory is likely to be used again.
Spatial locality: nearby memory is likely to be used soon.
The TLB benefits from locality because repeated access to the same pages
can reuse cached translations.
TLB Pressure
TLB pressure occurs when a program touches more memory pages than the TLB
can efficiently track.
This can happen with:
large working sets
random memory access patterns
many processes switching frequently
large data structures spread across many pages
High TLB pressure can slow a program even when enough RAM is available.
Huge Pages
One way to reduce TLB pressure is to use larger pages.
A normal page is often 4 KiB. A huge page may be much larger, such as 2 MiB.
With larger pages, one TLB entry covers more memory.
4 KiB pages:
many pages → many translations
2 MiB huge pages:
fewer pages → fewer translations
Huge pages are useful in some workloads, especially databases,
virtualization, and large memory applications.
Observing TLB Behavior
TLB behavior is usually observed through performance tools rather than
ordinary shell commands.
perf stat
perf stat <command>
Possible TLB-related events
perf stat -e dTLB-loads,dTLB-load-misses <command>
Available event names depend on the CPU and kernel.
You can list supported events with:
perf list
Connection to CPU Cache
The TLB helps the CPU find where memory is.
CPU caches help the CPU get the actual data quickly.
Virtual address
↓
TLB translates address
↓
Cache checked for data
↓
Data returned to CPU
The TLB accelerates address translation.
CPU cache accelerates data access.
Both are essential for fast memory behavior.
Conceptual Summary
The TLB is a fast CPU cache for address translations.
It prevents most memory accesses from requiring expensive page-table walks.